1. Technical Field
The present application relates to a network transfer technology for transferring data while saving the power, and cutting down the latency, as much as possible in a semiconductor system that can distribute loads such memory accesses.
2. Description of the Related Art
In order to distribute memory access loads over a semiconductor chip circuit, a semiconductor system circuit with a hierarchical memory architecture, in which a number of memories with multiple different access rates are organically coupled together with their implementation costs and processing performances taken into account, has been proposed. Among other things, to overcome the problem of overloads on a bus, researches and developments have been carried on to distribute the traffic among multiple transmission paths evenly using a so-called “Network on Chip” (which will be abbreviated herein as “NoC” and) which is a network in a semiconductor chip circuit.
As an NoC needs a number of memories and will dissipate a lot of power, it is important to cut down the power dissipation by relays (also called “routers”) in the NoC. Thus, a power gating technique, by which the routers selectively stop or resume their operation depending on whether or not they need to relay the traffic, has been proposed for that purpose.
“Evaluations of Run-Time Power-Gating of On-Chip Routers for CMP” (Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, and Hideharu Amano, Information Processing Society of Japan Research Report 2009-ARC-185, No. 2, October 2009 (herein referred to as “Non-Patent Document No. 1”) proposes a method for mitigating the startup time by routing because it often raises a problem when the routers need to resume their operation. Meanwhile, a technique for stopping or resuming the routers' operation on a fine grain unit basis has also been laid open to general public.